The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a back gate single-crystal flexible thin film transistor that is formed utilizing a controlled spalling process.
Mainstream thin film transistor (TFT) devices are comprised of amorphous or polycrystalline materials as the active channel materials, due to large area and low-cost processing compatible with low-cost substrates such as, for example, glass or flexible plastic. However, the performance of these devices (particularly mobility and therefore drive current and switching speed) is limited by the non-crystalline nature of the semiconductor active material. High performance devices may be achieved by crystalline semiconductors; however, the process of high performance crystalline transistors is on bulk semiconductor substrates; i.e., substrates that are entirely composed of one or more semiconductor materials.
Top gate thin film crystalline transistors made by controlled spalling has been previously proposed. Two aspects of these devices can be further improved. (1) In these top gate structures, gate dielectrics can be deposited on a spalled semiconductor surface. If thermal oxide needs to be used as the gate dielectric, it has to be done on the original semiconductor wafer surface by thermal oxidation. As such, this surface will be buried under the stressor layer after spalling. A stressor layer removal and spalled layer transfer process needs to be used to expose this channel surface for source/drain (S/D) formation after spalling. This process will subsequently enhance the complexity of TFT fabrication. (2) The top gate TFT has the gate and S/D regions on a same surface, which can result in complicated interconnect and wiring of a TFT array.